RTC clock synchronization buffer driver delay chip

The NB3N51044 is a precision low phase glitch clock generator that supports PCI Express and sRIO clocking requirements. The device accepts a 25 MHz fundamental mode parallel resonant crystal or a 25 MHz single-ended reference clock signal and generates four HCSL/LVDS differential outputs clocked at 100 MHz or 125 MHz depending on the frequency select input F_SEL. The NB3N51044 can be configured to bypass the PLL from the signal path using BYPASS and provide the output frequency through a divider network. All clock outputs can be enabled/disabled individually via hardware input pin OE. Additionally, the device can be reset using the master reset input pin, MR_OE#.