RTC clock synchronization buffer driver delay chip

The MC100LVEL34 is a low-skew divide-by-2, 4, and 8 clock generation chip specifically designed for low-skew clock generation applications. The internal dividers are synchronized with each other so that the common output edges are all precisely aligned. Only the VBB pin, the internally generated supply voltage, is provided for this device. For the single-ended input case, the unused differential input is tied to VBB as the switch reference voltage. VBB can also re-bias the AC-coupled input. When used, decouple VBB and VCC with 0.01 μF capacitors and limit current source or sink to 0.5 mA. VBB should be left open when not in use. The common enable (ENbar) is synchronous, so the internal divider is only enabled/disabled when the internal clock is already in a low state. This avoids short clock pulses on the internal clock when the device is enabled/disabled, which can happen with asynchronous control. Internal runt pulses can cause loss of synchronization between internal divider stages. The internal enable flip-flops are clocked on the falling edge of the input clock, therefore, all relevant specification limits are referenced to the negative edge of the clock input. On start-up, internal flip-flops are brought to a random state; a master clock reset (MR) input enables synchronization between internal dividers and between multiple LVEL34s in the system.

The MC10/100EL34 is a low-skew divide-by-2, divide-by-4, divide-by-8 clock generation chip for frequency division, specifically for low-skew clock generation applications. The internal dividers are synchronized with each other so that the common output edges are all precisely aligned. The device can be driven by differential or single-ended ECL, or by a PECL input signal if a positive supply is used. Alternatively, a sinusoidal source can be AC-coupled into the device by using the VBB output (see the "Interface" section of the ECLinPS datasheet DL140/D). If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground through a 0.01 F capacitor. The VBB output is suitable for use as a switching reference for the EL34 input in single-ended input conditions, so this pin only sources/sinks 0.5mA. The common enable (EN) is synchronous, so the internal divider is only enabled/disabled when the internal clock is low. This avoids short clock pulses on the internal clock when the device is enabled/disabled, which can happen with asynchronous control. Internal runt pulses can cause loss of synchronization between internal divider stages. The internal enable flip-flops are clocked on the falling edge of the input clock, therefore, all relevant specification limits are referenced to the negative edge of the clock input. On start-up, an internal flip-flop will reach a random state; a master reset (MR) input can synchronize the internal frequency divider as well as multiple EL34s in the system. The 100 series includes temperature compensation.