RTC clock synchronization buffer driver delay chip

CDCVF2310 High Performance 1:10 Clock Buffer for General Applications

CDCLVD1208 Low Jitter 2 Input Selectable 1:8 General Purpose LVDS Buffer

CDCE913 Programmable 1-PLL VCXO Clock Synthesizer with 2.5-V or 3.3-V LVCMOS Output

TPL5000 TPL5000 Nanopower Programmable Timer and Supervisor

3-channel output LVCMOS 1.8V buffer 8-TSSOP -40 to 125

The MC100LVEP111 is a low-skew 2:1:10 differential driver for clock distribution, accepting two clock sources into one input multiplexer. The PECL input signal can be differential or single-ended (if using the VBB output). The LVEP111 can use HSTL inputs when operating under PECL conditions. The LVEP111 is designed to guarantee low output-to-output skew. Optimized design, layout, and handling minimize skew within and between devices. To ensure the tightest skew, both sides of the differential output are equally terminated to 50Ω, even if only one side is used. If not all ten pairs are used, all output pairs are similarly terminated to the same package side, whether used or not. If no outputs are used on one side, leave these outputs open circuited (unterminated). This keeps output skew to a minimum. Failure to do so will result in a 10-20 ps skew margin loss (propagation delay) in the output being used.