Logic device/transceiver/encoder

4-Channel, 2V to 6V Buffer 14-SOIC -40 to 85 with 3-State Outputs

16-Channel, 1.65-V to 3.6-V Buffer with Bus Hold and 3-State Output 48-SSOP -40 to 125

The MC100EP016A is a high-speed synchronous, presettable, cascadable 8-bit binary counter. The structure and operation are the same as the MC100E016 in the ECLinPS series. The counter has internal feedback to the TCbar gated by the TCLD (Terminal Count Load) pin. When TCLD is LOW (or left open, in which case it is pulled to LOW by an internal pull-down), TCbar feedback is disabled, counting continues, and TCbar goes LOW, indicating a unity state. When TCLD is HIGH, TC causes the counter to reload automatically when TC = LOW, thus acting like a programmable counter. The Qn output does not need to be terminated for the counting function to function properly. To minimize noise and power dissipation, unused Q outputs should be left unterminated. COUT and COUTbar provide differential outputs from a non-cascaded counter or voltage divider application. COUT and COUTbar should not be used in cascaded configurations. Only TCbar applies to counter or divider cascaded chain outputs. A differential clock input has been added to improve performance. The 100 Series includes temperature compensation.